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FPGA Design • Sustainable Computing • Research

Engineering Smarter Systems for a More Sustainable Future.

I design and research FPGA-based systems, digital hardware architectures, and emerging computing technologies with a focus on efficiency, sustainability, and practical innovation.

  • SystemVerilog Design
  • FPGA Architecture
  • AMD Vivado
  • Hardware Verification
  • Sustainable Computing
  • Quantum Computing Research
About

Hardware engineering, grounded in real-world problem solving.

A’Yana Leonard is a U.S. Army veteran, FPGA and digital systems designer, and quantum computing research assistant with Altivatum. Her work explores sustainable computing, energy-aware hardware, parallel processing, AI acceleration, and emerging computing technologies. With an interdisciplinary background in technology, research, physics, mathematics, and business, she approaches engineering from both a technical and real-world problem-solving perspective.

U.S. Army

Veteran

Altivatum

Quantum Computing Research Assistant

Interdisciplinary

Tech • Physics • Math • Business

Featured Work

Selected FPGA projects.

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Sustainable FPGA Architecture

GreenChip

An energy-aware FPGA architecture that explores hardware-based monitoring, communication, environmental sensing, and intelligent power management for sustainable embedded systems.

  • SystemVerilog
  • AMD Vivado 2026.1
  • AMD Artix-7
  • UART & SPI communication
  • Activity & energy monitoring

Notable achievement

Successfully completed simulation, verification, synthesis, placement, routing, timing analysis, and FPGA bitstream generation.

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FPGA AI Acceleration

GreenMatrix

A parameterized FPGA-based matrix multiplication accelerator using a systolic array architecture, reusable processing elements, multiply-accumulate units, and a controller finite-state machine.

  • SystemVerilog
  • Parameterized systolic array
  • Multiply-accumulate architecture
  • Reusable processing elements
  • Matrix loader

Notable achievement

The 2×2 implementation achieved timing closure on an Artix-7 target with zero failing setup or hold endpoints. The architecture was designed to support future scaling to larger arrays.

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FPGA Parallel Computing

YanaGPU

A compact vector-compute GPU prototype and FPGA portfolio architecture featuring a four-lane SIMD arithmetic engine, an eight-entry vector register file, encoded operation control, and automated behavioral verification.

  • Four-lane SIMD compute
  • Vector addition & multiplication
  • Eight 64-bit vector registers
  • Self-checking SystemVerilog testbench
  • AMD Vivado

Notable achievement

Successfully implemented for an AMD Artix-7 target after redesigning the data interface to reduce physical I/O usage from 133 exposed ports to 50.

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Let’s build something meaningful.

Have a technical problem, research question, or ambitious idea? I’d be glad to hear what you’re working on.

Let’s Connect