Each project is carried from concept through simulation, verification, and full FPGA implementation. Explore the source on GitHub or expand each card for a deeper summary.
An energy-aware FPGA architecture that explores hardware-based monitoring, communication, environmental sensing, and intelligent power management for sustainable embedded systems.
Notable achievement
Successfully completed simulation, verification, synthesis, placement, routing, timing analysis, and FPGA bitstream generation.
A parameterized FPGA-based matrix multiplication accelerator using a systolic array architecture, reusable processing elements, multiply-accumulate units, and a controller finite-state machine.
Notable achievement
The 2×2 implementation achieved timing closure on an Artix-7 target with zero failing setup or hold endpoints. The architecture was designed to support future scaling to larger arrays.
A compact vector-compute GPU prototype and FPGA portfolio architecture featuring a four-lane SIMD arithmetic engine, an eight-entry vector register file, encoded operation control, and automated behavioral verification.
Notable achievement
Successfully implemented for an AMD Artix-7 target after redesigning the data interface to reduce physical I/O usage from 133 exposed ports to 50.
From proof-of-concept development to research partnerships, I’d be glad to explore what we can build together.
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